1. Technical Field of the Invention
This invention relates generally to error injection methods and apparatus used in testing electronic data processing systems, and more particularly, to the selective injection of parity errors into data resident within a data processor or memory for testing error detection and recovery systems.
2. Description of the Prior Art
In the past, errors have been injected into electronic circuits by probing circuit nodes to force connected circuitry to certain states indicative of errors. This can be done manually, or automatically. U.S. Pat. No. 4,759,019 to Bentley et al. discloses a programmable apparatus that injects errors by automatically short-circuiting voltage nodes within the system under test to ground or to a supply voltage in response to the system obtaining a particular state. U.S. Pat. No. 4,835,459 to Hamlin et al. describes a computer-controllable external device which, like the Bentley system, injects errors by applying voltage levels to pins or external circuit nodes of the unit under test. Error injection is triggered when a predetermined logic state exists on one or more of the externally-available circuit nodes.
Although straight-forward, the process of injecting errors by shorting circuit nodes can cause damage to circuits if voltage levels are not accurately applied. Moreover, this process is often not possible when highly integrated circuits are being tested, since most circuit nodes are not accessible to external probing devices. One common means of injecting errors into nodes that are not readily accessible involves the use of internal xe2x80x9cscan-setxe2x80x9d logic.
Scan-set logic usually includes a group of internal state devices which are interconnected to one another to form a shift register called a xe2x80x9cscan stringxe2x80x9d. Internal circuit nodes can be forced to logic levels by shifting (scanning) data into the scan strings from a device input to simulate an error condition. Generally, this scan will be performed after the system clock has been stopped. After the scan string is initialized to a particular state indicative of an error condition, the system clock is restarted. The injected error condition exercises the error detection and recovery logic.
Several complications exist with using scan strings to inject errors. Prior to injecting most errors using scan strings, the system clock must be halted as discussed above. This must be done at a precise time, so that the circuit is in the same logic state that would exist prior to a particular error occurrence during normal circuit operation. Stopping the clock so that the logic is in an exact state is difficult. Generally, it involves stopping the clock sometime before the logic is in the required state, then issuing single clock pulses until the logic is in the precise state. Calculating the required clock control, then administering that control during circuit test, is time-consuming and error-prone. Moreover, this process must be repeated for every error injected.
The above-described problems are accentuated when testing very complex circuits such as those associated with pipelined instruction processors. More specifically, testing parity-error detection and recovery logic in pipelined instruction processors has been particularly problematic in prior art systems for several reasons. In pipelined instruction processors, several instructions are in various stages of execution within the instruction processor at one time. If a parity error is detected on an instruction within the instruction processor, the instruction processor typically completes execution of all foregoing uncompleted instructions in the instruction stream, that is, the pipelined instruction processor is xe2x80x9cde-pipedxe2x80x9d. After the instruction processor is de-piped, the instruction that was corrupted is re-fetched from memory. Both the de-pipe and re-fetch processes require very complex logic sequences to perform. These sequences are dependent not only on the type of instructions which are resident in the pipeline at the time of the error, but also on the relative memory address of the re-fetched instruction.
The testing sequences may be further complicated when the instruction processor has one or more levels of cache memory. In many instruction processors, instructions are stored in two (or more) levels of cache memory including a second level cache that receives instructions from main memory, and a first level cache that provides the instructions into the instruction pipeline. In some instruction processors, a read buffer is also used. When a read buffer is used, a block of instructions are typically fetched from the second level cache and provided to the read buffer before the block of instructions are written to the first level cache. The read buffer is useful when, for example, the instruction processor uses certain prediction algorithms to predict which instructions will be needed in the future. Accordingly, when an instruction processor makes a request for a particular instruction, the instruction may reside in the main memory, the second level cache, the read buffer or the first level cache. Since it is often difficult to predict in advance where a particular instruction will reside when a request for the instruction is made, it can be difficult to write test procedures to test the error-detection and recovery logic for such instructions.
Instruction pre-fetch can also make it more difficult to test the error-detection and recovery logic of many data processing systems. During instruction pre-fetch, blocks of instructions are typically read up from the second level cache or main memory and stored in the read buffer and/or first level cache, before being supplied to the instruction processor. In some cases, the pre-fetched instructions are stored in an instruction queue in the instruction processor, which is useful in providing ready access to the pre-fetched instructions by the instruction pipeline. However, in such a system, it is often difficult to predict in advance where a particular instruction will reside when a request for the instruction is made. The requested instruction may reside in the instruction queue, the main memory, the second level cache, the read buffer or the first level cache. Accordingly, it is often difficult to write test procedures to test the error-detection and recovery logic for such instructions.
For many prior art data processing systems, such as those described above, completely testing the error-detection and recovery logic can require the execution of hundreds or even thousands of error injection test cases. Performing this testing using the scan-set and associated clock control operations described above is very time-consuming. As a result, many prior art systems required lengthy test schedules that are no longer feasible considering the short design cycles associated with modern-day development efforts.
According to the present invention, a system is provided for automatically injecting parity errors into instruction signals of a data processing system as the instructions are provided from a read buffer to a first level cache. The parity errors are selectively injected according to programmable indicators, each programmable indicator being associated with one or more instructions stored in the read buffer. The error-injection system also may include programmable operating modes whereby error injection will occur during, for example, every copy back from the read buffer to the first level cache, or alternatively, during only a selected copy back sequence. The system allows for comprehensive testing of error detection and recovery logic in an instruction processor, and further allows for comprehensive testing of the logic associated with performing a data re-fetch from the a second level cache or storage device.
In a preferred embodiment, the instruction processor is a pipelined instruction processor, although this is not required. Within the instruction processor, several instructions may be in various stages of execution at any given time. A parity error detection circuit is provided for detecting parity errors in instruction that are provided to the instruction processor. The detection of a parity error causes the instruction processor to complete execution of any other uncompleted instructions resident within the instruction processor pipeline before re-fetching the target instruction from memory. This is called xe2x80x9cde-pipingxe2x80x9d the instruction processor pipeline. The sequences required to de-pipe the instruction processor, and to re-fetch the instruction from memory will vary based on the type of instructions present in the pipeline at the time the error occurred, the relative location of the target instruction within a predetermined block of storage in memory, and other factors.
To increase performance, the instruction processor may have one or more levels of cache memory. In one illustrative embodiment, instructions are stored in two levels of cache memory including a second level cache that receives instructions from a main memory, and a first level cache that provides instructions to the instruction pipeline. A read buffer is also provided. The read buffer receives blocks of instructions from the second level cache, and copies the instructions to the first level cache in an instruction copy back sequence. During operation, a block of instructions are first fetched from the second level cache and provided to the read buffer. The fetched instructions may then be provided to the instruction processor directly from the read buffer. During a subsequent fetch from the second level cache, the instructions stored in the read buffer are xe2x80x9ccopied backxe2x80x9d to the first level cache before another block of instructions are loaded into the read buffer.
The error detection circuits of the instruction processor preferably provide an error signal when a parity error is detected in an instruction. Retry circuits are also provided for causing the instruction processor to discard the corrupted instruction and to again retrieve the discarded instruction from the second level cache or main memory in response to receiving the error signal.
To help test the error detection and retry circuits of the instruction processor, the present invention contemplates providing a parity error injection circuit coupled to the read buffer for selectively injecting parity errors into selected instructions as the instructions are provided from the read buffer to the first level cache during the copy back sequence. The parity error injection mechanism of the present invention may allow errors to be selectively injected into the instruction stream so that the error-recovery sequences of the instruction processor may be fully tested at full system clock speeds.
Preferably, the present invention allows parity errors to be selectively injected into instructions based on indicators which are programmed using, for example, a scanable interface. Selected indicators preferably specify one or more locations or words within the read buffer. The indicators are programmed based on predetermined test criteria. This allows the parity error injection tests to be tailored to obtain specific test coverage.
It is contemplated that the parity error injection system may have several modes of operation. In a first illustrative mode of operation, parity errors may be injected during a single copy back sequence. This is called the xe2x80x9csingle shot modexe2x80x9d. During subsequent copy back sequences, no parity errors are injected. In a second illustrative mode of operation, called the xe2x80x9ccontinuous modexe2x80x9d, parity errors are continuously injected during all copy back sequences. In either of these modes, the programmable indicators may select only certain instructions in the block of instructions that are transferred from the read buffer to the first level cache. In addition, the programmable indicators may select specific parity bits within the selected instructions. The various operating modes of the invention preferably allow for complete test coverage of the many hardware sequences associated with parity error detection and recovery in a pipelined instruction processor.